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Integrated Circuit (IC) with aging-robust ARMv2 processor, Operational amplifier, and test structures for pixels; Core team: Sill Torres, F.; Oliveira, C.F.R.; Silva, A. S., Vecchia, V.A.S Technology: GF130 (cmrf8), 2017. |
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IC with structures for pixels; Core team: Sill Torres, F.; Pinto, P.H.K.M; Oliveira, C.F.R.; Guimarães, M.V., Technology: TSMC 0.18, 2016. |
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IC with Pipelined ADC and test structures for pixels Team: Sill Torres, F.; Pinto, P.H.K.M; Oliveira, C.F.R.; Guimarães, M.V. Technology: TSMC 0.18, 2016. |
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IC with test structures for hybrid pixel array Core team: Belmonte, P.N.A, Monteiro, D. W. L., Sill Torres, F., Technology: TSMC 0.18, 2016. |
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IC with test structures for hybrid pixel array Core team: Monteiro, D. W. L. ; Sill Torres, F. ; Miranda, P.H.S. ; Cruz, C. A. M., Technology: ams C35B4, 2013. |
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IC with test structures for hybrid pixel circuits, a RISC processor and circuits that focus on the reliability enhancement based on the approach „Bulk-BICS Core team: Monteiro, D. W. L. ; Sill Torres, F. ; Salles, L. P. ; Maeda, R. K. V.; Miranda, P.H.S. ; Cruz, C. A. M.; Assunção, P.C., Technology: ams C35B4, 2013. |
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IC with test structures for integrated image sensors and circuits that enhance the reliability based on the approach „Alternating Module Activation“ (AMA), Core team: Monteiro, D. W. L.; Salles, L. P. ; Sill Torres, F. ; Miranda, P.H.S. ; Cruz, C. A. M. ; Assunção, P.C., Miranda, P.H.S. ; Cruz, C. A. M., Technology: ams C35B4, 2011. |