Mixed Gates

The idea behind the  Mixed Gates design technique is the combination of advantages from gate level and transistor level approaches. That is, high accuracy and applicability for a standard cell design flow. In addition, the Mixed Gates approach merges both Dual Threshold Voltage-CMOS (DVT-CMOS) and Dual Tox-CMOS (DTO-CMOS) approaches.

Transistor leakage as well as delay highly depends on the transistor parameters threshold voltage (Vth), gate oxide thickness (Tox), and channel depletion (NDEP). Against this background, two types of transistors were defined by extensive simulations. The first type, fast switching transistors L-Vt/To with high leakage currents, uses low Tox and low NDEP, which results in low Vth and short delay. The second transistor type H-Vt/To has high Tox and high NDEP, which results in high Vth. The latter transistors switch slower but have lower gate oxide leakage as well as reduced sub-threshold leakage. HVTO gates consisting solely of H-Vt/To transistors and LVTO gates consisting solely of L-Vt/To transistors have been implemented (see figure below). At this stage, leakage reduction based on the idea of DVT/DTO-CMOS approaches can be performed.

However, the Mixed Gates approach offers two additional gate types, which are called standard Mixed Gates (MG) and Fast Mixed Gates (F-MG). F-MG gates contain few H-Vt/To transistors at adequate positions so that delay is equal to corresponding LVTO gates but leakage is lower. Therefore, LVTO gates are not used any further because they can be replaced by F-MG gates without any drawback on performance due to equal delay but lower leakage. Finally, MG gates contain mainly H-Vt/To transistors, so that gate delay is in between the delay of F-MG and HVTO gates. The figure above depicts four variations of a NOR2 gate and the table classifies mixed gate types qualitatively. When applying the Mixed Gates approach, a design is initially implemented with F-MG gates only. Then, as many gates as possible are exchanged by appropriate MG and HVTO gates so that maximum delay is not increased. That is, critical paths consist solely of F-MG gates whereas all other paths apply a combination of the three gate types so that path delays do not exceed critical path delay.

Thus, the Mixed Gates approach offers three advantages:

  • larger amount of low leakage devices within a design than possible in DVTO approaches
  • reduction of both main sources of leakage currents: gate oxide leakage Igate and sub-threshold leakage Isub
  • no drawback on performance compared to the original designs which consist of fast and high leakage devices


Related Publications

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Improvement of Technology Parameters for a Dual-Vth/Tox Technology
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Sill. F.,
Untersuchung und Reduzierung des Leckstroms integrierter Schaltungen in Nanometer-Technologien bei konstanten Performanceanforderungen

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Engel, K.; Kalinowski, T.; Labahn, R.; Sill, F.; Timmermann, D.,
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International Symposium on System-on-Chip 2006, pp.111-114, ISBN: 1-4244-0621-8, Tampere, Finland, November 2006.

Sill, F.; Cornelius, C.; Kubisch, S.; Timmermann, D.,
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Sill, F.; Salomon, R.,
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Salomon, R.; Sill, F.,
Biologically-Inspired Optimization of Circuit Performance and Leakage: A Comparative Study
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Sill, F.; Cornelius, C.; Timmermann, D.,
Statistische Analyse des Zeitverhaltens von CMOS Schaltungen und Modellierung von Parametervariationen,

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Sill, F.; Cornelius, C.; Timmermann, D.,
Reduzierung des Leckstromverbrauchs mit gemischten Gattern in Deep Submicron Technologien

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Sill, F.;Timmermann, D.,
Total Leakage Reduction by Observance of Parameter Variations

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Sill, F.;Grassert, F.;Timmermann, D.,
Total leakage power optimization with improved Mixed Gates

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Sill, F.;Timmermann, D.; Cornelius, C.
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Engel, K.; Kalinowski, T.; Labahn, R.; Sill, F.; Timmermann, D.
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Reducing Leakage with Mixed-Vth (MVT)

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Sill, F.;Grassert, F,;Timmermann, D.
Low Power Gate-level Design with Mixed-Vth (MVT) Techniques

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Sill, F.;Grassert, F,;Timmermann, D.
Reduzierung des Leistungsverbrauchs in Deep Submicron Designs

11. Symposium Maritime Elektrotechnik, Elektronik und Informationstechnik, Rostock, Germany, June 2004.

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